The power supply to a core power domain is switched off to reduce power leakage in standby mode. However, switching off the power supply to the core power domain causes loss of information from the pad configuration registers that are implemented in the core power domain. The pad configuration registers may need to be restored when the power supply to the core power domain is switched back on. No external memory is accessible until the pad configuration registers are restored, for example. Furthermore, only a limited number of inputs and/or outputs are allowed at the boundary between the core power domain and an always-on power domain to avoid routing congestion.
Conventional D flip-flop implementations can have power leakage from the chip as high as 5.6 μW. Moreover, conventional D flip-flop implementations can occupy a chip area as large as 0.05 mm2. Conventional placement of the pad configuration registers in the always-on power domain leads to undesirable place and route congestion. Conventionally, software interactions are needed to restore the pad configuration registers.